In digital data systems it is often necessary to transfer data between asynchronous clock domains. A clock domain is a group of logic circuits where all of the clocked storage elements, such as flip-flops and registers, are clocked by the same clock. Two clock domains are asynchronous with respect to each other if their respective clocks have no fixed phase relationships. For example, a processor that is operating at a clock frequency of 2 GHz may need to send 64 bits of data to a PCI-X bus that is operating at a clock frequency of 133 MHz. In this case, the two clocks do not have a fixed phase relationship with each other so the two clock domains are asynchronous.
Another example is a graphics processor that needs to transfer data between a system bus operating at 533 MHz and the graphics memory that is operating at a data rate of 800 MHz. The two clock domains have no fixed relationship with each other, and thus are asynchronous.
Digital data is most commonly stored in flip-flops or RAMs. A group of flip-flops is also known as a register. A register may be comprised of any number of flip-flops but groupings of 8, 16, 32, and 64 flip-flops are common. A register composed of 8 flip-flops would typically have 8 inputs and 8 outputs. All of the flip-flops in a register are clocked by the same clock. Registers are lower in storage density compared to RAMs, but are much faster in operation. Thus, registers are often used when data must be stored and retrieved quickly.
Since registers are composed of flip-flops, the data at the input of the register is sampled by the clock edge, as in a flip-flop, and stored in the register. However, also as in flip-flops, the data must be stable for a period of time before and after the clock edge to avoid metastability. The period of time before the clock edge is called the setup time and the period after the clock edge is called the hold time.
Conventional registers cannot be used to store data if the data is coming from an asynchronous clock domain. Because of the unknown clock phase relationship between the sending clock and the receiving clock, the data cannot be guaranteed to satisfy the setup and hold requirements of the receiving register. Metastability may ensue if a register is used to store data coming from an asynchronous clock domain. Once a register goes into a metastable state, the outputs of the register are neither logical 0s nor logical 1s, as expected. Furthermore, there is no limit on the duration of the metastable state and no guarantee the eventual stable outputs will have any relationship to the asynchronous data which triggered the metastable event.
To avoid metastability, complex signaling protocols can be used to indicate the data is stable and may be clocked into the receiving register. Many elaborate protocols and circuits have been devised to signal the availability of stable data for transfer between asynchronous clock domains. Some of these are described below.
A first in first out memory (“FIFO”) is another mechanism used to transfer data across asynchronous clock domains. Data is written into the FIFO by the source clock domain logic and read out by the destination clock domain logic. The delay between writing and reading insures the validity of the data.
The costs of these complex protocols or FIFOs are additional latency in data transfer and more logic circuits. The additional latency is undesirable for high performance systems and additional logic is undesirable for both power consumption and chip size. Thus there is a need for a high speed and low latency method and apparatus to transfer multiple bits of data across asynchronous clock domains.
The most common method of synchronizing an asynchronous signal using flip-flops is to connect two flip-flops in series. The asynchronous signal is connected to the data input of the first flip-flop. The output of the first flip-flop is connected to the input of the second flip-flop, possibly with a small delay gate inserted. Both flip-flops are clocked with the clock of the receiving clock domain. Then the output of the second flip-flop is treated as the synchronized version of the asynchronous signal.
This method depends on the usually finite duration of the metastable state to guarantee the second flip-flop will not sample an undefined output from the first flip-flop. Unfortunately, this technique does not extend easily to multiple bits of data. The random resolution of the metastable state means that a register will not settle to a stable output that is related to the original input data. So while a second register will most likely sample stable output from a first register that is coming out of a metastable state, that data will have no resemblance to the original asynchronous data sampled by the first register.
Existing solutions either create new clocks that do not have edges close to each other or devise protocols to insure data is stable before being sampled by a receiving register.